I'm trying to get a better understanding of how the NMOS works when a negative voltage is applied to the gate.
So I currently understand that the $P^-$ substrate is lightly doped with such a material from the group III elements. This allows for an excess of holes in the material.
What I don't understand is why these holes get attracted to the SiO2 insulator, creating a $P^+$ Accumulated channel under the material, when a negative voltage is applied.
Why is that negative voltage pulling the holes towards the SiO2 insulator? I would like to be able to visualize what exactly is happening.