I was having a discussion with a colleague. Imagine a circuit with ideal components. The circuit is a capacitor divider (1uF and 1pF capacitors) with the midpoint being pulled down to GND by a 1Meg resistor. We drive the circuit with an ideal 1kHz 1V square wave. What is the maximum voltage drop across $C1$?
My colleague argued that at $t=0$, the capacitor $C1$ will see the entire 1V drop across it, since the midpoint is weakly biased to GND by the resistor.
I argued that the largest voltage drop the capacitor will ever see will be equal to the divider across $Z1/(Z1 + Z2)$. Where $Z1 = C1$ and $Z2 = C2||R1$. The value will be almost 0V since $Z1 << Z2$. The R1 bias resistor is not able to effectively hold the V_mid node at GND, current will mostly flow through C2 (since its resistance is so low at 1Khz).
Who is right? I tired simulating the circuit but it was not enough to convince my friend. Can someone provide a more rigorous physics explanation of what happens at t=0? I tried asking in the EE stack exchange but got no traction.