In this article from 2007, Moore talks about the end of his Law. Can someone throw more light as to how the finite speed of light and the atomic nature of mater are related to the end of Moore's law?

  • $\begingroup$ en.wikipedia.org/wiki/Grace_Hopper : "She started handing out pieces of wire which were just under one foot long (11.80 inches), which is the distance that light travels in one nanosecond. She gave these pieces of wire the metonym "nanoseconds."[21] She was careful to tell her audience that the length of her nanoseconds was actually the maximum speed the signals would travel in a vacuum, and that signals would travel more slowly through the actual wires that were her teaching aids " ... And find the total amount of length your information goes through (ram->bus->pipelines...->bus->ram) $\endgroup$ Nov 7 '13 at 17:04

The moore's (empirical) "law" states that the number of transistors in a chip increases exponentially (doubles every 2 years). So the question is : is there a hard limit in the number of transistors in a chip? Or, in other words : Are there limits on the size of a chip and on the size of transistors? Indeed there are (almost).

The matter is made of atoms, so you can't decrease the size of transistors indefinitely by just scaling down the same design (manufacturing issues aside). You can modify the design (that's what Intel & others are doing) but there is still a limit on the number of atoms : it's (seemingly) impossible to design a transistor made of a single atom...

Now, you could say "OK, let's increase the chip size instead". It turns out that it's also limited. Again, cost aside (pure silicon isn't cheap), the the signals must be transmitted across the chip in less than a clock cycle, so that the chip stays in sync. The information isn't travelling any faster than the speed of light, but what is the size of a chip that gets its information in less than 1/2 clock cycle at, say, 5GHz? That's 30mm. And that's assuming electric potential travels in silicon at speed of light in vacuum (it doesn't), and that's assuming it's OK to have signals 180° phase-shifted (it isn't).

So yes, that's quite a limit!

There is also the option to go 3D and start growing again "vertically". However the thermal flux will be the major problem here: a CPU die typically outputs 100W in a 1cm² chip. That's 1MW/m2, and that's quite a lot (and close to the limit of known materials). Now suppose you manage to double the number of "planes" every 2 years, and after 6 years you're doing 8MW/m2 (about what's allowed by copper with water cooling). After 10 years, your typical CPU would burn 3200W...

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    $\begingroup$ "the the signals must be transmitted across the chip in less than a clock cycle, so that the chip stays in sync." is not correct. Clock signals themselves, for example, are distributed through a distribution tree of buffers with every locality getting very closely timed clock edges by the tree being delay balanced. The physical layout of the chip can minimize signals that need to travel a long distance. And adding a 1 clock delay can often deal with those that must go a long way. Also, a large chip can be broken up into clock-domain subsections, resynchronizing at the boundaries. $\endgroup$ Feb 28 '14 at 0:51

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