When looking at today's logic ICs, for example CPUs, those seem to consist of a very thin and dense layer of transistors, wired by a large amount of "metal" layers on top to complete the circuit.

For flash memory chips, on contrast, it seems that the memory cells can be stacked to several layers on top of each other.

So with all the never-ending need of scaling logic circuits, why not just back up a little on dimensional scaling, and stack the transistors on top of each other? I first thought of maybe thermal reasons - it is already hard to cool the single layer we have today - but more transistors may be clocked with lower frequency, lower voltage and thus lower power dissipation. Also a 3D-layouted circuit will greatly benefit from shorter wiring, thus it may be inherently faster and lower power.

So what is the show stopper on stacking circuits on logic ICs ?

  • $\begingroup$ The assumption that speed (clock frequency) can casually be traded for parallelism (more transistors) is shakey. $\endgroup$
    – Chad K
    Nov 22, 2023 at 17:34
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    $\begingroup$ There is an electrical engineering SE that might be an appropriate place for this question. $\endgroup$ Nov 22, 2023 at 17:44
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    $\begingroup$ Interesting question. As far as I believe to know, CPUs are one-layer transistors because the process of creating is by etching the surface. Once this is done, there is no layer above that could be etched. Do you have any reference that flash memory chips are stacked? $\endgroup$ Nov 22, 2023 at 17:45

2 Answers 2


The short answer is "they're working on it."

Modern lithography techniques typically etch and dope a layer of monocrystaline silicon. They typically do not add layers of it (in fact, I have not found any evidence in my research to suggest it can be done). This restricts traditional ICs to one layer.

I did some looking into FLASH memory, but had limited success in finding examples of it being built up with many layers of silicon. I did come across two patterns that had layers. Mutli-level FLASH memory does not add vertical layers. Instead, it adds multiple levels of charge per cell. If you have 8 possible levels of charge, you can store 3 bits in that cell. There was also an interesting technology called 3D XPoint (brand name: Optane). This was not FLASH, but rather another form of non-volatile RAM using resistivity to encode bits. It was truly 3d stackable, being made out of components that could be layered on via deposition. Of course, it was discontinued with poor market penetration.

3d circuits is a hot topic today. Just a few months ago, this article was released with an assessment of many technologies in development to support 3d printing. The common pattern for all of them is that they don't rely on the traditional Si semiconductor. They rely on other semiconductors which support deposition. All of these technologies are still in their infancy, compared with the traditional lithography capabilities of modern chip manufacturers.

  • $\begingroup$ Once the gears of my brain getting loose on about that topic, what about manufacturing very, very thin layers of one-face etched transistors and gluing them one over another, just geometrically, without connecting them, as this would need precision unfeasible yet? $\endgroup$ Nov 22, 2023 at 18:45
  • $\begingroup$ @GyroGearloose That is definitely a real thing. It is used when area is at a premium and also used to minimize the length of interconnects. $\endgroup$
    – Cort Ammon
    Nov 22, 2023 at 18:49
  • $\begingroup$ FLASH memory already uses multiple layers for sure. Here is a currently produced product with hundreds of layers: au.pcmag.com/storage/95306/… $\endgroup$
    – dronus
    Feb 13 at 20:11

There are several reasons:

  1. Depth of field for optical lithography.

The smaller the line widths, the smaller the depth of field for focusing patterns onto a substrate. Fabrication begins on an optically flat wafer but as oxides and interconnects are added, the topography of the surface has hills and valleys that are not in focus. The fix to this is to deposit a thick layer of insulator (spin glass or thick oxide deposition) and then carefully polish the insulator flat. It's expensive.

  1. Silicon wafers are cheap, epitaxial growth is expensive.

It's much easier to stack finished circuit boards or chips in 3D to save space. While the first transistor layer uses relatively inexpensive fabrication techniques, the subsequent layers will require high quality crystalline silicon layers that require expensive epitaxial deposition in addition to the planarization already mentioned.

Overall the reward is not worth the expense.

  • $\begingroup$ Another reason is that for high performance circuits, getting rid of the heat is a challenge. A single layer is optimal for this. $\endgroup$
    – John Doty
    Nov 22, 2023 at 19:20
  • $\begingroup$ You say "epitaxial growth is expensive". Do you refer to the growth of a "virgin" layer of silicon over an already etched and finished layer of the surface? $\endgroup$ Nov 22, 2023 at 19:21
  • $\begingroup$ @GyroGearloose - You can’t grow epi on some random surface. Now thinning and stacking might work(ish), but then heat remains a huge issue. $\endgroup$
    – Jon Custer
    Nov 22, 2023 at 19:39
  • $\begingroup$ @JonCuster I think laying another layer of silicon is not a problem, but the point is doing it without completely destroying what is beneath. Can't it be done by interlacing some sort of "wax", something soft enough not to destroy what is already there, and voluminous enough to separate it from whatever brutality is required to establish the next upper layer? $\endgroup$ Nov 22, 2023 at 19:48
  • $\begingroup$ My guess would be that the sheer amount of additional transistors added by going 3D may allow for very low frequency and thus low power operation, reducing the thermal problems vastly. At least for circuits where transistors can be traded for frequency, which is true for paralelizable operations. $\endgroup$
    – dronus
    Feb 13 at 20:07

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