How does a capacitor 'transfer' voltage/charge from one plate to the other when the circuit is open? I am new to electrical engineering, electronics and capacitors specially.
I am having trouble understanding why in the following circuit, the voltage is the same in both plates, acting as a wire, when they plates are separated by a dielectric, and there is no loop.
Electronic engineers would give formulas around impedance and why at high frequencies the capacitor has very low impedance so it acts as "wire".
But still, I don't understand how the voltage is transferred from one plate to the other. It just can't fit my mind.
Is there any way from a beginners perspective I can understand this phenomenon?

 A: I'm going to address your question by writing two answers: one that analyzes a slightly modified but essentially equivalent system from the point of view of circuit analysis, and the other that considers that exact collection of components as a physical system.
Part I: Using circuital laws
In this answer I will reduce the system to a circuit model where the usual circuit laws work. This will give us some insight on what to expect when analyzing the actual physical system where ordinary circuital laws do not apply.
1 Adding stray capacitance to 'ground'
Instead of considering an absurdly big resistance representing the finite conductivity of the medium between the dangling terminals (which is what some simulators/solvers do, but would make no sense from the physical standpoint when the terminals are dangling in a vacuum), I will add a stray capacitance that represents the mutual capacitance between the top conductor and the ground (terminal). This is not an academic trick: even when the ground is represented by 'the other wire' we can easily model the interaction between conductors by means of an added capacitance. As a matter of fact, the mutual capacitance C' per unit length of a system of two identical cylindrical conductor of diameter d (the wires), separated by a distance D (in air or in vacuum) is
$$
C'_{12}=\frac{\pi \epsilon}{ArcCosh(D/d)}\approx \frac{\pi \epsilon}{log(D/d)}
$$
where the approximation is valid when the distance between the wires is much greater than their diameter.
For example, for two wires 1mm in diameter separated by a distance of 10 cm in air (or vacuum) we get a mutual capacitance of about 5 pF per meter. Let's say our circuit has wires 10 cm long: we can model the mutual capacity between such wires with a lumped 0.5 pF joining the top and bottom conductor. This will close the circuit and reinstate Kirchhoff's Laws and Order so that we will be allowed to treat the problem using the usual elementary techniques of circuit theory.
Once we model out system with this circuital model we can solve it for different kinds of excitation. I will only consider an abrupt "DC" step (from 0 to 12V) and a sinusoidal source (at 240Vrms no less!). I will not consider a pulsed input because the property of continuity of voltage across a capacitor would lead to negative values in the output voltage that IMO would distract from the physics. I am also (initially) dropping the series resistance because it does not add anything at this level of abstraction, but I will reintroduce it later because it gets interesting when analyzing the physical model.
Step excitation ("DC")
This is the circuit that models our simplified system with a DC step excitation represented by the connection of the battery at t=0. (Please keep in mind that in the following I will be referring to the capacitor in the position occupied by C1 as "Cseries" and to C2 as "Cout" - my simulation ran in a single file and I do not want to keep track of the unique capacitor names used in each circuit).

And this is the result of the simulation in LTSpice (with both capacitor parasitic conductances set to zero) on an interval of half a second.

We see that the output voltage seems to 'immediately' reach 12V and to replicate the input voltage (here shown with a little offset to make it visible) apparently in an exact manner, while the big 47uF capacitor appears to be completely uncharged. In reality, since we cannot afford infinite energy, the output capacitor cannot change instantaneously its voltage, but starts from the initial condition (which I assumed to be 0V) and rises exponentially with an exceedingly small time constant. With such a small value of parasitic capacitance to ground, even if we add a series resistance of 1meg to slow this transient down, it will still last less than a microsecond (and in any case it will be way smaller that the time constant required by the much bigger series capacitance to charge up).
After this very brief transient, the output voltage seems to equal to the input 12V, but this is the result of the extreme asymmetry in the values of C1 and C2. In reality, in this model (that is a legitimate model of the actual physical system in a lab) the two capacitors C1 and C2 form a capacitive divider and not all of Vin appears across C2. With 0.5pF and 47uF, we can say that Vout = 0.999999989...Vin = Vin.
What is happening here is that both capacitors are gradually charging up from their initial 0V condition to the final equilibrium voltages determined by the capacitive divider ratio; the smaller one reaches nearly Vin while the much bigger one barely goes above 0 volts. For the actual movement of charges refer to my second (upcoming) answer.
Here is a 'hand-drawn' plot of the input and output voltages when I greatly exaggerate the duration of the initial transient and the repartition of voltage of the capacitive divider:

Of course, if C2 were much much bigger or C1 much much smaller, an appreciable amount of voltage would appear across C1. (For example, if C1 = C2, you would only see half of the input voltage at the output - the other half would appear across C1).
Sinusoidal Steady-state excitation
If we use a sinusoidal excitation we still see what appear to be Vout being identical to Vin

As in the previous case, this is but a consequence of the extreme unbalancing of the capacitive divider. SInce we are well within the realm of circuit theory, we can compute the reactances and see that the voltage repartition is the same we would have with a resistive divider with Z1= 68 ohms and Z2 = 6.4 Gohm: practically all of the voltage (apart from a few nanovolts that in the real world end up drowned in noise) will drop across Z2, i.e. all of Vin ends up at the output and fundamentally none across Z1.

Keep in mind that when we consider a sinusoidal steady state we are implicitly assuming the circuit has been running for an infinite time and the initial transient has died out well before the dinosaurs even walked the Earth.

2 Closing the circuit on a voltmeter's internal resistance
Another way we can create a valid circuital model for the system you propose, is by adding the input impedance of the instrument measuring Vout. If we use a voltmeter with an input resistance of 10 Mohm, we will be able to close the circuit and reinstate Kirchhoff's laws even without (the now unimportant, but I will nevertheless model it) stray capacitance
DC step excitation
The DC excited loaded circuit is quite interesting in that it shows how the instrument is requiring a current that will slowly charge the series capacitor Cseries (from the voltage set by the capacitor divider - that is just a few nanovolts), up to the point where all of the voltage will drop across it and none will be left at the output.
If there were no Cout at all, from the point of view of circuital laws, we could say the the series capacitor cannot instantaneously change its voltage, so the whole 12V would instantly appear on the other side at t=0+ (more on this in my other answer) and from then on the exponential charging of Cseries will proceed to reduce this voltage until it is reduced to zero and all of it appears across Cseries.
By adding Cout we create a capacitor divider whose output is shunted by a large resistor, but note that the dynamics here is dictated by the charging of Cseries.

We have already seen that - with the given values of 47uF and 0.5pf - the capacitive divider would result in almost zero voltage across Cseries and almost all 12V across Cout. So, the 'further charging' of Cseries appears to start from zero, and it will be characterized by a time constant of about 470 seconds. We therefore should expect the output to rise almost instantly to (nearly exactly) 12V and then slowly decaying to zero in about five taus, or  40 minutes. The following plot shows the output voltage in dark red and the voltage across the series capacitor in Dijon mustard color.

Note that if we look at our voltmeter for just a few seconds after connecting the source we can still be under the impression that the outout voltage is simply replicating the input voltage step.

But now we know better: the output is actually reaching a value that is essentially determined by the capacitor divider, and it does so almost instantly because the charging process is dominated by the exceedingly low values of Cout and the internal resistance of the generator.  What Cout sees, in fact, is the parallel of the voltmeter resistance with the internal resistance of the generator (plus the ESR of the capacitors and the sheer resistance of the copper wires). The resulting time constant will be very small (it will still be under 1 microsecond even if we added the 1meg series resistance!). After that step-like fast rise, the charging of the 47uF series capacitor is so slow that the output voltage seems almost constant, but now we know that, as the voltage across Cseries rises, Vout is inevitably decreasing, heading towards zero volts.
Sinusoidal steady-state excitation
In the circuit with sinusoidal excitation, the 'discharge' and 'recharge' of the main capacitor translates into an almost imperceptible phase shift, that adds to the imperceptible attenuation of the resultant impedance divider. I will only show the input and output waveform in the same scale and the voltage across the 47uF capacitor at steady state multiplied by 10 thousand times (its only 2.4mV peak, it would have been invisible on the same scale) to show that it is periodically charging and discharging around the 0V level.

The above simulation was recorded after it had run for 8.4 second to allow for the transient to die off.
Unlike the case with a single-shot step input, the presence of the resistive load does not 'eventually drag the output to zero' because we are continually dragging the carpet from under its feet, alternately charging and discharging the capacitors in the circuit.
Obviously, if instead of a very high multimegaohm resistance you close the circuit using a much smaller resistor, the impedance divider equilibrium changes making less voltage to appear at the output and more voltage to appear across the series capacitor.
This is also the reason why you can detect stray voltages with a voltmeter across a pair of open terminals, but as soon as you connect them to a load, that voltage 'collapses'.

3 Adding a series resistance to the (capacitively and/or resistively) closed circuit
Adding a large series resistance will help us better seeing the processes of charge and discharge. To get an even better view of what is actually going on, let's change the values of the output capacitor to a less extreme value. We can also consider the circuit with all elements: the shunt capacitance and the voltmeter's internal resistance.

If we do not attempt to measure the voltage (thus removing Rmeter from the above schematics), after an exponential rise the voltage plateaus to the value set by the capacitive divider (at equilibrium no current flows and no voltage drop will result across the series resistance). The above capacitive divider would produce an appreciable attenuation, with the output reaching, at equilibrium, the value Vout =10/(10+2) Vin = 10V. This value would not be reached immediately because  the process of charging up Cseries to 2V would require at least 4-5 time constants dominated by the 1meg series resistance.

But if we connect the voltmeter, adding the output shunt resistance Rmeter, we will no longer be able to reach the full capacitive divider level of 10V because part of the charge that was intended for Cout is routed to ground via the resistor. Cout can still try to charge up, but the process is inverted before it is able to reach 10V due to the increased voltage across Cseries that is now using Rmeter to hog all the charges it needs to charge to the fully 12V of Vin. When Rmeter is present, Cseries no longer has to depend on Cout to do what it wants and so, instead of settling for a meager 2V, goes the whole way to 12V.

In a way the act of charging Cout is akin to trying to fill a bathtub with a leaking (or missing) tub stopper and a slowly closing faucet. In the above plot we can clearly see the sudden rise in voltage at the beginning that is due to the fast charging of the capacitive divider (this is dominated by the smaller Cout); but then the series capacitor keeps on charging, even if at a slower pace, progressively reducing the voltage applied to the parallel of Cout and Rmeter until after a long exponential decrease (dominated by Cseries), Vout eventually becomes zero.
With a sinusoidal input, subsequent charging and discharging bring a steady state equilibrium where the voltages across the output terminals can be easily computed in terms of the voltage divider formed by the impedances Z1 and Z2. With the 'domesticated' values used here we get Z1 = Rserie + j Xseries = 10 meg - i 67.7, Z2 = Rmeter // j Xout = 9.99998 meg + j 15.7 k which leads to what is basically a 10/11 resistive divider.  And in fact the simulation shows all sinusoids essentially in phase, with Vout = 309V and Vz1 = 31V (peak values).

Unlike the previous plot of sinusoidal waveforms, the scale is the same for all waveforms.
The complete circuit with actual capacitance values
If we now change the values of Cseries and Cout back to 47uF e 0.5pF we see the initial rise to be so fast as to become a vertical step, and then a discharge that is soleley due to the value of Cseries (and the resistance it 'sees'). When we look at the output on a timescale of a few seconds, we see what appears to be a sudden step that replicates almost exactly the step in the input voltage

Even more interestingly, the values for the sinusoidal steady state voltages are the same as before because the impedances that form the voltage divider are dominated by the resistors (Rseries dominates the series with Cin because it's much bigger than Xcin, while Rmeter dominates the parallel with Cout because it's much smaller than Xcout). This means that we will still lose some 30 volts in the peak amplitude of the output voltage.
This loading effect is something that needs to be taken in account when measuring electric circuits with suboptimal instrumentation (like a 10megaohm input-resistance voltmeter for circuits with megaohm resistors).
The limit case when C2 goes to zero and Rmeter goes to infinity
Now that we have seen how a circuit that closely (or even better) represent your system behaves, we can try to tackle the theoretical problem where there is no load resistance at all and the stray capacity to ground (or the mutual capacity of the two conductor) is considered to be zero.
This will be treated in my other answer. For the time being, let me tell you that the circuit ceases to be... a circuit, in that we no longer can apply Kirchhoff's current law. We will need to consider the role of surface charges, both on the conductors and the plates of the capacitor, and we will see that there will be different charges on the two sides of the capacitor's plate.
