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I have a question regarding to hardware signal. There is a rule says "smaller is faster". In the link it says that that

  1. In high-speed machines, signal propagation is a major cause of delay;

Is there a diagram shows the details of this? e.g. the x-axis is number of registers/memory unit and the y-axis is the delay/time

  1. In most technologies we can obtain smaller memories that are faster than larger memories. This is primarily because the designer can use more power per memory cell in a smaller design;

Why does more power make the signal faster? Isn't that the speed of current the same regarding to the same medium?

I suppose that there may be a simple formula for resolving my problem.

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  • $\begingroup$ @DDuck: If it's of speed of light, then why more power faster? Isn't that still same speed? $\endgroup$
    – Kindred
    Nov 30, 2018 at 0:20
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    $\begingroup$ Perhaps better suited for Electrical Engineering, but two comments. Yes, signal propagation causes delays, not just on boards but chips as well. But, this is often fairly minor compared with what I think (2) should say, that smaller transistors, given the same drive current to the gate, will turn on/off faster than a larger transistor since their capacitance is smaller. That is, device scaling may reduce switching delays (although often one also reduces the currents to limit power dissipation so it can be a wash). $\endgroup$
    – Jon Custer
    Nov 30, 2018 at 1:08
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    $\begingroup$ @JonCuster This is the sort of question where the choice of Stack Exchange site may reflect the sort of answer the OP is looking for. The fact that the OP posted here suggests that they're looking for an answer based in physical principles such as basic electromagnetic theory, energy considerations, etc. $\endgroup$
    – DanielSank
    Nov 30, 2018 at 4:49
  • $\begingroup$ @DanielSank - I understand, which is why it was a small part of a comment. The fact that a new user posted here probably doesn't mean much at all actually. I'm not really sure where Carver Mead would have asked his questions on CMOS scaling, but he was in the Engineering and Applied Science department at CalTech... $\endgroup$
    – Jon Custer
    Nov 30, 2018 at 13:45

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The OP is asking specific questions about a general statement from a general computer architecture course.

In high-speed machines, signal propagation is a major cause of delay;

Computers are made of clocked registers. It takes a specific amount of time for an output to change from low to high and high to low, which is impacted by technology, fan out, fan in, voltages, etc.

74AS74 switching characteristics

The 74AS74 is a D-flip-flop. It has a $t_{PHL\ MAX}$ of 8ns and $t_{PLH\ MAX}$ of 9ns. So if the output was fed to the input, the output would take 17ns to transition from H to L to H, which would give you a minimum frequency of 58.8MHz. Minimum of 6ns would give you maximum frequency of 166.6MHz and stated Minimum frequency is 105MHz.

Toggle flip-flop

So no logic, just feeding output to input and maximum clock rate is 166MHz. Ignoring setup and hold times, no fan-out, no fan-in, no gates with their own propagation delays, no race conditions, etc. Add these factors and the maximum clock rate must slow down.

So getting the logic from the input side of a chip to the output is a major cause of delay in any computer chip. In any design, there will be a critical set of chip delays, which govern the maximum clock rate for the design.

A chart would be meaningless. You are trying to extrapolate the number of gates with delays, when the actual computer logic governs the maximum clock rate.

In most technologies we can obtain smaller memories that are faster than larger memories. This is primarily because the designer can use more power per memory cell in a smaller design;

As memory technology evolved, the physical area of a transistor got smaller. In the same size die more transistors could be placed. More transistors means more power, but at the same time a smaller transistor means less power. At the same time a smaller transistor, so propagation delays are less and clock speeds can increase.

But this is not where the author is going. This snippet is taking the author out of context. He is justifying the use of high speed memory in cache to maximize throughput.

From Memory Hierarchy Design

Memory heirarchy design is based on three important principles:

Make the Common Case Fast

Principle of Locality

Smaller is Faster

The above principles suggest that we should try to keep recently accessed items in the fastest memory. Because the smaller memories are more expensive and faster, we want to use smaller memories to try to hold the most recently accessed items close to the CPU and successively larger (and slower, and less expensive) memories as we move away from the CPU. This type of organization is called a memory hierarchy. Two important levels of the memory hierarchy are the cache and virtual memory.

Cache is a small amount of high speed memory consuming higher power.

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  • $\begingroup$ Thank you boss rat! I should connect the words more power to cache from now on. I don't understand what $\rm{P}$ in $\rm{t_{PHL}}$ means, but from your ["]...when the actual computer logic governs the maximum clock rate. [."] can I make a conclusion that: if more registers used in a given instruction set architecture, then logic (gate) involved must increase so slow down follows? $\endgroup$
    – Kindred
    Dec 1, 2018 at 4:54
  • $\begingroup$ Not really. And it's too complex to deal in an answer or comment. Designers use pipelining and cache to optimize the instruction queue. More registers increase complexity but allow code to run out of registers (fastest). L1 cache feeds registers (fast), L2 cache feeds L1 (slightly slower), main memory feeds L2, and storage feeds main memory. A memory hierarchy. Everything is a tradeoff. $\endgroup$ Dec 1, 2018 at 17:48

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