It is known that in a transistor, like the FET below, it has an 'on' state when current flows from source to drain, and an 'off' state when there is no current flowing between junctions.
This current is mediated by gate voltage, shown as $V_{GS}$ in the diagram below. When $V_{GS}$ is greater than some threshold $T$, current flows and the transistor is on.
My question is this: how does the gate voltage mediate between on and off? That is, if $V_{GS}$ is applied to a transistor, that transistor will be in state $S$ - this means that the $V_{GS}$ must also be in state $S$ (on or off). If this is the case, then the transistor's state tells you nothing more than knowing the gate's state. Is it just a feed-forward from previous transistors?