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I was having a discussion with a colleague. Imagine a circuit with ideal components. The circuit is a capacitor divider (1uF and 1pF capacitors) with the midpoint being pulled down to GND by a 1Meg resistor. We drive the circuit with an ideal 1kHz 1V square wave. What is the maximum voltage drop across $C1$?

My colleague argued that at $t=0$, the capacitor $C1$ will see the entire 1V drop across it, since the midpoint is weakly biased to GND by the resistor.

I argued that the largest voltage drop the capacitor will ever see will be equal to the divider across $Z1/(Z1 + Z2)$. Where $Z1 = C1$ and $Z2 = C2||R1$. The value will be almost 0V since $Z1 << Z2$. The R1 bias resistor is not able to effectively hold the V_mid node at GND, current will mostly flow through C2 (since its resistance is so low at 1Khz).

Who is right? I tired simulating the circuit but it was not enough to convince my friend. Can someone provide a more rigorous physics explanation of what happens at t=0? I tried asking in the EE stack exchange but got no traction. enter image description here

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  • $\begingroup$ "current will mostly flow through C2 (since its resistance is so low at 1Khz)." - ??? The reactance of C2 at $1\,\mathrm{kHz}$ is about $159\,\mathrm{M\Omega}$ $\endgroup$ – Alfred Centauri Nov 20 '17 at 21:01
  • $\begingroup$ Look at it this way, $1\,\mathrm{V}/1\,\mathrm{M\Omega} = 1\,\mathrm{\mu A}$ so, in $0.5\,\mathrm{ms}$, the voltage across $C_1$ cannot change by more than $0.5\,\mathrm{mV}$ and thus, essentially all of the voltage appears across $R_1$. The capacitor $C_2$ is essentially irrelevant. $\endgroup$ – Alfred Centauri Nov 20 '17 at 21:10
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The R1 bias resistor is not able to effectively hold the V_mid node at GND, current will mostly flow through C2 (since its resistance is so low at 1Khz).

This is where your argument goes off of the rails. The impedance of $C_2$ at the fundamental frequency is

$$Z_{C2} = \frac{1}{2\pi\cdot 1\,\mathrm{kHz}\cdot 1\,\mathrm{pf}} \approx 159\,\mathrm{M\Omega} \gg 1\,\mathrm{M\Omega}$$

so it simply isn't the case that the 'resistance' of $C_2$ is low at $1\,\mathrm{kHz}$. Nonetheless, you are correct that the voltage across $C_1$ is small at $t=0+$.

Assuming the capacitors are initially uncharged and if we ignore $R_1$, the equivalent capacitance of the series connected $C_1$ and $C_2$ is just under $1\,\mathrm{pF}$. I see that you set the rise time of the voltage source to be $1\times 10^{-18}\,\mathrm{s}$ and so the charging current during the rise time is

$$I_+ \approx \frac{1\,\mathrm{pF}\cdot 1\,\mathrm{V}}{1\times 10^{-18}\,\mathrm{s}}= 1\,\mathrm{MA}$$

which means ignoring $R_1$ is valid during this time. At the end of the first $1\times 10^{-18}\,\mathrm{s}$, the voltage across $C_2$ is just under $1\,\mathrm{V}$ and the voltage across $C_1$ is just under $1\,\mathrm{\mu V}$.

But after the first $1\times 10^{-18}\,\mathrm{s}$, $C_1$ continues to charge (through $R_1$) while $C_2$ discharges. After the first $0.5\,\mathrm{ms}$, the voltage across $C_1$ has increased to about $0.5\,\mathrm{mV}$.

So the maximum voltage across $C_1$ is not at $t=0+$ and that maximum voltage is dominated by the effect of $R_1$ rather than $C_2$.

Note that since the square wave source has a 0.5V DC component, the average voltage across $C_1$ should go to about $0.5\,\mathrm{V}$ in about $5\,\mathrm{s}$.

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  • $\begingroup$ You are correct about Z_C2 if this was a sine wave. Assuming an ideal square wave the rising edge of the square is infinite and so Z_C2 would appear as a dead short since the frequency component are so high - would it not? I only use 10^-18 because I couldn't get simulation to run with 0 rising edge. Maybe I did something wrong. $\endgroup$ – EasyOhm Nov 20 '17 at 22:55
  • $\begingroup$ @Gonzik007, impedance doesn't work that way. The very notion of impedance assumes sinusoidal excitation. If you apply a voltage to a capacitor that is the sum of two or more sinusoidal voltages of different frequencies, you can't define the impedance of the capacitor since each frequency component 'sees' a different impedance. For a voltage ramp like in your simulation, it's better think in the time domain where $i(t) \approx C\frac{\Delta v}{\Delta t}$. $\endgroup$ – Alfred Centauri Nov 20 '17 at 23:01
  • $\begingroup$ @Gonzik007, you can't actually apply an ideal square wave voltage to a capacitor unless you allow current impulses (infinite current for infinitesimal time). Computer simulations in the time domain generally require finite amplitude and finite minimum time step. $\endgroup$ – Alfred Centauri Nov 20 '17 at 23:07
  • $\begingroup$ Thanks for your replies so far. So even with a square wave that has a very fast rise time of 10^-18 [sec] and a voltage source that can provide the current what happens to the rising edge of the waveform when it hits the capacitor? If I think of the edge as an infinite sum of odd sine harmonics would the higher harmonics see a low impedance across C2 at t=0 when the capacitor is not charged? Would this result in a larger initial current across C2 compared to the steady state when most passes through R1? $\endgroup$ – EasyOhm Nov 21 '17 at 0:35
  • $\begingroup$ @Gonzik007, in the context of ideal circuit theory, the voltage across the capacitor is fixed by the voltage source. Since the capacitor current is proportional to the derivative of the capacitor voltage, the higher frequency harmonics produce a proportionally large current than the lower frequency harmonics (regardless of charge). $\endgroup$ – Alfred Centauri Nov 21 '17 at 1:21
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On a time scale that is short compared to the time constant of the network, the resistor hardly matters and the network acts as a capacitive divider. You are right that you can write the impedance as you did and it will tell you that almost the entire voltage will briefly appear across the smaller capacitor.

To see this you have to run the simulation with time steps much smaller than 1 micro second.

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Possibly a good way of analysing the circuit without initially doing any sums is to apply a step pulse of $+1\,\rm V$ to the circuit and see what happens as the capacitance of capacitor $C_2$ is varied from $1 \,\mu\rm F$ through $1 \,\rm nF$ to $1 \,\rm pF$.

enter image description here

The time scale on the graphs is seconds.

The top graph confirms your idea that the series capacitors charge (almost) instantaneously (assuming very small voltage source resistance) acting as a potential divider network.
The series capacitors store equal charges in this initial state.

In the bottom two graphs the initial voltage across $C_2$ is almost the supply voltage and the voltage across $C_1$ becomes progressively smaller compared with the supply voltage as $C_2$ gets smaller.

Once the capacitors are charged then the voltage across $C_2$ decreases with a time constant of $\rm 2 \,\mu F \times 1\, M\Omega = 2\, s$ for the top circuit and approximately $\rm 1 \,\mu F \times 1\, M\Omega = 1\, s$ for the bottom two circuits.

On the time scale of your circuit driven by a $1 \, \rm kHz$ square wave that drop in voltage across $C_2$ is negligible and so the voltage across $C_1$ is very close to zero.

All this indicates is that if you removed the $1\,\rm pF$ capacitor in your circuit you would see very little difference when compared with the circuit which contains the $1\,\rm pF$ capacitor.

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