How does power consumption vary with the processor frequency in a typical computer? I am looking for an estimate on the relationship between the rate of increase of power usage as the frequency of the processor is increased.
Any references to findings on this would be helpful.
 A: To add to the "linear with frequency" point, there is also an additional factor. As that "dynamic power" increases, the temperature of the die will increase and this will also increase the leakage current through the millions of transistors, which will cause more dissipation (termed "static power")
There's a long Anandtech thread taking lots of values and pulling them apart into their static and dynamic contributions which results in the following graph:

The slight kick up in static power at higher clock speeds is (as I understand it) as a result of the higher die-temperature.
A: For example, the Pentium 4 2.8 GHz has 68.4 W typical thermal power and 85 W maximum thermal power. When the CPU is idle, it will draw far less than the typical thermal power. The power consumed by a CPU, is approximately proportional to CPU frequency, and to the square of the CPU voltage:
$P=CV^2f$
Taken from here: http://en.wikipedia.org/wiki/CPU_power_dissipation
A: Power consumption is about linear with frequency.  

The processor contains millions of complementary FETs as shown. When the input goes low the small capacitance gets charged and it will hold a small amount of energy. A same amount is lost during the charging. When the input goes high again the charge will be drained to ground and be lost. So with each level change $n$ Joules are lost. If the frequency is 1 MHz then this switching occurs 10$^{6}$ per second, and $n$ 10$^{6}$ Joules will be lost per second. If the frequency is 1 GHz that loss will be  $n$ 10$^{9}$ Joules.
Notice that the energy in a capacitor is $\frac{C \cdot V^2}{2}$, so the dissipation varies quadratic with voltage; running the processor at half the voltage will reduce power with 75 %. 
This leads to the equation tuğrul also mentions:  
$ P = c \cdot V^2 \cdot f + P_S $
where $c$ is a scaling constant, with the dimension of capacitance (F). $P_S$ is the static power dissipation Martin refers to, which is the power at a zero clock frequency.
A: For a given circuit in a given technology, power increases at a rate proportional to $f^3$ or worse.  You can see by looking at the graph in @Martin Thompson's answer that power is superlinear in frequency.
$P=c V^2 f + P_S$ is correct, but only superficially so because $f$ and $P_S$ are functions of $V$ and $V_{th}$ (the threshold voltage.)  In practice voltage, threshold voltage, and frequency are always changed together.  Given a chosen voltage there is a maximum frequency at which you can run your circuit.  Running any faster will result in bad data.  But you would never set the frequency much below the maximum frequency for a chosen voltage because then you are just wasting power.
Let's ignore the leakage (static) power and just focus on the dynamic power, $cV^2f$.
By the alpha approximation
$$
f \propto \frac{(V-V_{th})^\alpha}{V}.
$$
Here $\alpha$ is a technology-dependent constant that accounts for velocity saturation.  $\alpha$ would be 2 for no velocity saturation (for example in 1000nm technology and older), and approaches 1 with complete velocity saturation.  In 250nm technology it was somewhere between 1.3 and 1.5.  In 45nm it might be somewhere between 1.1 and 1.4.
Before 1995 one might assume that $\alpha$ was 2 and that $V \gg V_{th}$, in which case $f \propto V$ so $P \propto f^3$.  But in 2013 technology (45nm and below) not only is $\alpha$ more like 1.3 than 2, but $V$ is now only slightly larger than $V_{th}$.
Further the static power $P_S \propto e^{(-V_{th}/V_o)}V$, which means that choosing voltage, threshold voltage and frequency is now a nonlinear constrained optimization problem.  (Given a fixed maximum power optimize for the highest achievable frequency or given a fixed required frequency optimize for the minimum power.)
Here are three very good papers that discuss the optimization procedures and their consequences:
Gonzalez, Gordon, Horowitz; Supply and Threshold Voltage Scaling for Low Power CMOS; IEEE JSSC, 32(8), 1997.
Brodersen, Horowitz, Markovic, Nikolic, Stojanovic; Methods for True Power Minimization; IEEE/ACM Int'l Conf on CAD, pp. 35-42, 2002.
Horowitz, Alon, Patil, Naffziger, Kumar, Bernstein; Scaling, Power, the Future of CWWW-VLSI, IEEE Int'l Electron Devices Meeting, 2005.
This paper clearly shows the nonlinear increase of power consumption with an increase of frequency:
Miyoshi, Akihiko, et al. "Critical power slope: understanding the runtime effects of frequency scaling." Proceedings of the 16th international conference on Supercomputing. ACM, 2002.
A: See also a video that covers this topic presented by one who knows:
Tim Mattson (Intel): Introduction to OpenMP: 02 part 1 Module 1, YouTube, December 6, 2013
Starting at 3:34 he derives the equation:
$$ P = C V^2 f .$$
Then he says at 5:14 referring to halving the frequency:

[...] frequency scales with voltage, but you know [leakage...], so let's say the voltage goes not half, lets say it goes to .6.

The equation on the slide shown there is as follows:
$$ P_{reduced} = 2.2 C ⋅ (0.6 V)^2 ⋅ f/2 $$
$$ = 2.2C ⋅ 0.36 V^2 ⋅ f/2 $$
$$ = (2.2 ⋅ 0.36 ⋅ 0.5) CV^2f $$
$$ = 0.396CV^2f. $$
That means a power reduction to 40 % at half of the frequency in his case.
