What is the probability of quantum tunneling occurring in this CPU? You may have noticed over the last few years that Moore's law is no longer applying to the real world.
This observation states that over the history of computing hardware, the number of transistors on integrated circuits doubles approximately every two years.
However, as microprocessors in computers have continued to become smaller, the architecture size has become incredibly small:- the new Skylake architecture to be released by Intel will use 14 nm semiconductors.
We are beginning to reach the limit in size where the information being passed is still completely reliable.
Would it be reasonable to ask how much quantum tunneling would occur in a semiconductor 5 nm in length? We can assume that in this CPU
Voltage = 1.2 V
Current = 63 A
I enjoy physics, but I'm not that great at it; I'd love to hear the results! Even if massive approximations!
 A: Dims is almost correct, in that you would only see resonant tunnelling effects at very low temperatures.
In other words, at very low temperatures the electrons will sit at very well defined energy levels within the transistors.  Under certain biases (voltages), the energy levels on either side of the thin barriers between devices will line up, and electrons can tunnel between the devices without any resistance.  This would give rise to sharp "spikes" in the current at very specific voltages, and the electrons would "spread" freely between adjacent devices.
At higher temperatures, tunnelling does still occur, but the electons are spread over a broad range of energies rather than in well-defined states.
As such, you don't see the resonant "spikey" behaviour discussed above.  Rather, you'll just see a general broad leakage of electrons between devices.
Now, in terms of quantifying this, take a look at any good textbook on heterostructure devices, for example, Chapter 2 in P. Harrison "Quantum Wells, Wires and Dots", 3rd Ed. Wiley (2009).
The probability (from 0 to 1) of an electron tunnelling through a single, thin barrier is given by:
\begin{equation}
T(E) = \frac{1}{1 + \left(\frac{k_b^2 + k_w^2}{2k_bk_w}\right)^2\sinh^2(k_bL)}
\end{equation}
where $L$ is the length of the barrier separating regions of the device, $E$ is the energy of the electron and $k_w$ and $k_b$ are the wave vector (proportional to momentum) of the electron within the device, and the decay constant of the wave function in the barrier respectively.
These are given by:
\begin{equation}
k_w = \frac{\sqrt{2m_e^* E}}{\hbar}
\end{equation}
and
\begin{equation}
k_b = \frac{\sqrt{2m_e^* (V-E)}}{\hbar}
\end{equation}
respectively, where $m_e^*$ is the effective mass of the electron and $V$ is the barrier potential.
Let's consider electrons with energy half-way up the barrier (i.e., $E = V/2$) for a simple estimate of the "average" tunnelling probability.  Therefore, $k_w = k_b$ and the tunnelling probability simplifies to:
\begin{equation}
T(E) = \frac{1}{1 + \sinh^2(k_bL)}
\end{equation}
Now, to get a rough estimate (I don't have the parameters to hand), take an effective mass of $0.3m_0$, and a barrier potential of 1 eV.
This gives $k_b = 2\,\text{nm}^{-1}$.
Now, calculating the tranmission probability for a range of barrier lengths gives the following:

It is, therefore (with this set of parameters!) unlikely that we'd see any tunnelling effects until the barrier thickness drops below a couple of nm.
Note, though, that the effects would be much more significant for lower effective mass, lower barrier potential or higher electron energy.  I'll happily update the plot if anyone feels like providing more realistic parameters.
Note also, that other classical breakdown effects like thermal leakage, and practical issues with quality of materials are likely to cause equally (or more) significant problems!
