Timeline for Simulating Toffoli Gates with Fredkin Gates with no garbage bits
Current License: CC BY-SA 3.0
8 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Aug 3, 2017 at 16:57 | comment | added | Sam Jaques | The idea was that you have only Fredkin and NOT gates, plus as many ancilla bits as necessary, but at the end of the computation all ancilla bits must return to their original values. | |
| Aug 3, 2017 at 9:29 | comment | added | Norbert Schuch | What else do you allow for? Only classical gates, or are quantum gates allowed as well? What about 2-(qu)bit-gates, e.g. CNOT? (Since you are talking about fan-outs, CNOTs don't seem so far-fetched.) | |
| Aug 2, 2017 at 19:04 | vote | accept | Sam Jaques | ||
| Aug 2, 2017 at 18:57 | vote | accept | Sam Jaques | ||
| Aug 2, 2017 at 18:58 | |||||
| Aug 2, 2017 at 17:19 | comment | added | user122423 | This site may not be the best fit for this question; maybe Electrical Engineering or Computer Science would be better? | |
| Aug 2, 2017 at 17:18 | answer | added | Craig Gidney | timeline score: 5 | |
| Aug 2, 2017 at 17:01 | review | First posts | |||
| Aug 2, 2017 at 17:19 | |||||
| Aug 2, 2017 at 16:59 | history | asked | Sam Jaques | CC BY-SA 3.0 |