The complete explanation takes a few lectures - it is simply impossible to provide this amount of information as an answer.
Very general explanation:
Let's take a look at NMOS transistor (the one shown in the schematic attached to the question). It has 4 pins which you can force potentials on:
In order to understand how the channel is formed, it is enough to examine the cross section under the gate which forms a Metal-Oxide-Semiconductor (MOS) capacitor (the Gate may be made of metal or polysilicon; the distinction is not important for grasping the basics):
In nMOS capacitor, the bulk consists of p-type silicon. p-type silicon is characterized by a free carriers which (effectively) have positive charge - holes.
Applying positive potential to Gate (positive with respect to Bulk) will create an electric field pushing the holes deeper into the bulk (along positive $x$ axis in the scheme above). This repulsion of free carriers away from the interface will create a "depletion region" under the gate - a region with will contain (effective) net negative charges. However, since this negative charge is represented by an ionized acceptor impurities which are built into Silicon's lattice, this charge is not free and can not contribute to current.
Further increase in Gate's potential will cause the attraction of bulk's minority carriers (electrons) to the interface. These carriers are free and can contribute to a lateral current under the gate in presence of a lateral electric field. The voltage at which the amount of attracted minority carriers becomes appreciable is called the Threshold Voltage of Inversion.
The inversion layer is formed under the gate by bulk's minority carriers, which are attracted to the interface by a strong electric field created by Gate-to-Bulk voltage.
The best reference I've ever seen for studying the basics of (applied) semiconductor physics is this site (containing lecture notes by Professor Chenming Calvin Hu).