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Gate (poly-Si + $SiO_2$) and $p^{-}$ silicon operate as capacitors.

But how are voltages and charges applied? In order for inversion to occur, there should be charges formed in poly-Si, right? How does it work?

Or if I am mistaken, what is the process? (Both NMOS and PMOS would be appreciated.)

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Perhaps electronics.stackexchange.com is a better home? –  Qmechanic Jan 13 '13 at 7:50
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@Qmechanic, not sure about this. He asks about semiconductor physics, not EE applications. –  Vasiliy Aug 4 '13 at 15:46

2 Answers 2

The complete explanation takes a few lectures - it is simply impossible to provide this amount of information as an answer.

Very general explanation:

Let's take a look at NMOS transistor (the one shown in the schematic attached to the question). It has 4 pins which you can force potentials on:

  1. Gate
  2. Bulk
  3. Source
  4. Drain

In order to understand how the channel is formed, it is enough to examine the cross section under the gate which forms a Metal-Oxide-Semiconductor (MOS) capacitor (the Gate may be made of metal or polysilicon; the distinction is not important for grasping the basics):

enter image description here

In nMOS capacitor, the bulk consists of p-type silicon. p-type silicon is characterized by a free carriers which (effectively) have positive charge - holes.

Applying positive potential to Gate (positive with respect to Bulk) will create an electric field pushing the holes deeper into the bulk (along positive $x$ axis in the scheme above). This repulsion of free carriers away from the interface will create a "depletion region" under the gate - a region with will contain (effective) net negative charges. However, since this negative charge is represented by an ionized acceptor impurities which are built into Silicon's lattice, this charge is not free and can not contribute to current.

Further increase in Gate's potential will cause the attraction of bulk's minority carriers (electrons) to the interface. These carriers are free and can contribute to a lateral current under the gate in presence of a lateral electric field. The voltage at which the amount of attracted minority carriers becomes appreciable is called the Threshold Voltage of Inversion.

In summary:

The inversion layer is formed under the gate by bulk's minority carriers, which are attracted to the interface by a strong electric field created by Gate-to-Bulk voltage.

References:

The best reference I've ever seen for studying the basics of (applied) semiconductor physics is this site (containing lecture notes by Professor Chenming Calvin Hu).

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Usually, the Bulk of an NMOS is connected to the lowest voltage in the circuit, for an NMOS and the highest voltage in the circuit, for a PMOS. Then, depending on the value of this voltage and the Source-to-Bulk voltage of this transistor, a Threshold Voltage is defined, which is also called Turn On Voltage in some cases(especially in the digital circuits).

For an NMOS, in a typical case, the Bulk is connected to the ground, and hence is at 0 V. Depending on the process being used, the threshold voltage varies, and if we assume Source-to-Bulk voltage is 0, the transistor turns on when a voltage of $V_{th}$ is applied to the Gate terminal.

The flow of this process is as such: As you apply the voltage to the gate, poly-Si and p substrate form the two plates of a parallel plate capacitor, the holes in the p substrate are repelled(or cancelled by electrons being attracted from the lower parts of the bulk), and a depletion region is formed. Any further application of voltage above $V_{th}$ forms an n-channel(hence an NMOS) between the Source and Bulk n-wells of the device, allowing the flow of electrons between the two terminals.

The complete opposite occurs in a PMOS, where you apply a lower voltage to the Gate and repel the electrons on the n-substrate, forming a p-channel.

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