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When electronics/computer companies design a new chip, processor/ memory card/ or a solar cell, do they study the effect of cosmic rays on such electronically sensitive materials? If not, why not?

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The effect of CRs on electronics will increase with time. As the electronics shrink, we will be fitting more bits per unit area. As such, there will be less charge necessary to define a bit (how many electrons or holes signal that a bit is 1 or 0). Since one CR event will deposit a given amount of charge, the probability that a bit will flip (or the number of flipped bits) will increase with time.

A related fact is that Intel patented a CR detector attached to a chip (see here for a moderately useful article on it).

Pierre Auger noted about 100 years ago that CRs are not exactly the singular events that we think of. In particular, he noted that CR events at two locations 1 km apart have a high coincidence proving the existence of what we now call extensive air showers (EAS). Only sufficiently high energy cosmic ray primaries will create a shower that makes it all the way to the surface, although the rate here at the surface is still quite high. The point of all of this is that if you measure a CR event right next to your computer chip, it is quite likely that your computer chip was hit and may have been affected as well. The process in the Intel patent (which has no production plans that I'm aware of, I did meet a guy who was testing something that I imagine was a prototype of this on the side of mountain - higher elevation => more CRs) would then redo the last set of calculations before the event when an event was measured under the assumption of a particularly high probability of an error in the calculation.

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Cosmic rays do have noticeable affect on electronics. The most prevalent effect is from memory bit flips (known as "soft errors").

The degree of significance of the effect depends on the application. A typical soft error rate for static RAM is in the region of 400 FITs/Mbit [1]. (Failures in time=failures per billion device hours) So if you have 1 Gb of memory per chip and 1000 chips, then expect 0.4 flips every hour. This is precisely the reason that a lot of applications require ECC on their memories.

[1] footnotes: Part of the rate is from alpha particles from decay of materials of or near the chip (this is the smaller of the two major components). Also, the rate is quite a lot higher for DRAMs, which is why DIMMs with ECC exist.

Soft error rates are quoted at sea-level because the effect of being closer to space is non-trivial; which is pretty much proof right there that the effect is from cosmic rays.

There are effects on logic gates too, but this is usually not worked around for two reasons. (1) It is very difficult and/or expensive to do, however there is much research into redundant/fault tolerance circuits (2) when a bit flip occurs on a combinational path, it would have to coincide with exactly when the output of the path is observed (e.g. at a flipflop) which reduces the observability of the effect.

Finally, there is an effect known as single event latchup (SEL). I'm not certain my conception of the mechanism is correct, but as I understand is, a cosmic ray can ionize the path from source to drain of a transistor which will then conduct current regardless of voltage on the gate until the current goes away. I.e. it remains in that state until the power rail is powered down; hence "latchup". This is obviously much more rare, but real.

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For the most part cosmic rays do nothing to consumer electronics.

This is not to say that they can't flip bits or even damage elements, but the rate for such effects is very, very low.

Radiation effects are routinely observed in electronics placed in accelerator experimental halls (where the radiation levels are at lethal-dose-in-minutes levels when the beam is on). Ones that I have observed include

  • darkening of plastic scintillator and acrylic light guides
  • killing pixels on consumer closed circuit cameras used to allow operators to monitor activities in the hall and visually clear the area before allowing the beam to resume
  • circa weekly random crashes on DAQ boards that would run for months at a time while the beam was off. (No way to certainly rule of data loads as the cause of this, but the rate seemed to correlate with the beam current)

Note that the beam dump radiation monitors were calibrated to 1 Mrad/hr and often registered sustained rates around 10 krad/hr. Intensities in the other parts of the hall fell off to very reasonable levels like 100 rad/hr.

Note that the beam cutoff circuitry connected to the beam-dump radiation monitors worked reliably in a intense radiation environment for years.

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It is far from true that the rate of bit flipping is low. It depends on the application. A typical soft error rate for static RAM is in the region of 400 FITs/Mb [1]. (Failures in time=failures per billion device hours) So if you have 1 Gb of memory per chip and 1000 chips, then expect 400 flips every hour. This is precisely the reason that a lot of applications require ECC on their memories. [1] footnotes: Part of the rate is from alpha particles from decay of materials of or near the chip; also, the rate is quite a lot higher for DRAMs, which is why DIMMs with ECC exist. –  ThePopMachine Jul 23 '12 at 15:37
    
Additional comment of interest: Soft error rates are quoted at sea-level because the effect of being closer to space is non-trivial. –  ThePopMachine Jul 23 '12 at 15:41
    
please consider editing. –  ThePopMachine Jul 23 '12 at 15:43
    
@ThePopMachine I have to admit that the last time I investigated these rates closely was several mask sizes ago. On the whole I think that you have the making of a very good answer of you own there and that you should get credit for it. –  dmckee Jul 23 '12 at 15:45
    
Done, plus more interesting details, I hope. –  ThePopMachine Jul 23 '12 at 16:10
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