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I have the following circuit. All the inverters are ideal CMOS.

Circuit

I need to draw the waveforms for each point (A, B, D, E, Vo), given that waveform at input.
What I want to ask is if what I did so far is correct?

Waveforms

Thank you for your time. (And sorry for the poor quality of the images)

Edit:

Thank you for your response.

So, is this correct? (It is how I understood your response)

enter image description here

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I'm not going to migrate it, as I think it is OK here, but this might have been better on http://electronics.stackexchange.com/. –  dmckee May 24 '11 at 0:28
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1 Answer

up vote 3 down vote accepted

I'm not sure why the resistor to ground from B is there, but you are incorrect at point D, the capacitor doesn't pass the DC level as you've indicated. It's a high-pass filter with C and R, so basically you need to move the DC-level on the Vd plot to ground - but keep the two transients like you've plotted them. That is, the curve should start at ground and dip at the down-transition of Vb then make a similar transient upswing after Vb goes up.

This question should be on the electronics SE instead..

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I recommend LTSpice from Linear, a free graphical interface to the electronics simulator Spice. There you can easily whip up circuits like the above and probe what happens if you are unsure (and you of course get quantitative answers as well). –  BjornW May 24 '11 at 0:50
    
Thank you. I edited my question, and if you would be so kind to tell me if I understood correctly, please. –  iuliux May 24 '11 at 11:05
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Yes, you understood correctly. VD will always tend to 0 in the steady state. Transitions of VB will drive momentary spikes in VD (negative VD spike for a high-low transition of VB, and positive VD spike for a low-high transition of VB). –  Vintage May 24 '11 at 17:16
    
And are there known the values of the highest and lowest points? –  iuliux May 24 '11 at 17:38
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then VE will depend on if the spikes at VD will be high enough to turn the inverter. it depends on the capacitor and resistor and the gate design, but I guess the qualitative result they want is that some part of the transients at VD will make the inverters turn and give you a short pulse (while the transient is above a trigger-threshold). –  BjornW May 24 '11 at 17:47
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